(1) Field of the Invention
The present invention relates generally to interlevel dielectric polishing on semiconductor wafers, and more particularly to a wafer edge seal that limits exposure of polyimide layers to contaminants during polishing.
(2) Description of the Related Art
Polishing of semiconductor wafers is an important part of the total process of manufacturing integrated circuits. Integrated circuits are manufactured on silicon substrates by depositing layers upon layers of different materials, and one after another in a serial fashion within precise specifications. Each conductive layer is separated and insulated from each other by means of interlevel dielectric (ILD) insulating materials. Since each conductive layer consists of features and facets, e.g., metal lines of irregular shapes and dimensions, such features and irregularities manifest themselves as "bumps"or "steps" through the covering interlevel material. When such layers are added on top of one another, steps of progressively higher dimensions are produced. As it will be apparent to those skilled in the art, this is exacerbated even more as the number of levels in the interconnect technology is increased in today's sub-micron technology. The resulting unevenness or the irregular nature of surfaces ultimately lead to reliability problems due to the difficulty of depositing metal on such non-planar surfaces.
There is thus a need to smoothen or planarize the interlevel or ILD surfaces. For this purpose, prior art teaches several different methods of planarization. Some commonly used methods include such techniques as BPSG reflow, planarization with resist, or SOG planarization. In BPSG reflow, a layer of borophophosilcate (BPSG) glass is deposited and then heated to a temperature of greater than 900.degree. C. The heating step causes this material to soften and flow, providing a smoother surface as described, for example, in S. Wolf, "Silicon Processing for the VLSI Era," vol. 2, Lattice Press, Sunset Beach, California, 1990, p. 196. However, the temperatures used in this process are too high if aluminum, the most common metallization material, has already been deposited on the wafer. Also, BPSG reflow is most effective for narrow indentations, that is, very small areas of the ILD surface. Broad indentations and spaces in the surface are not made planar, and thus BPSG reflow does not provide for adequate "global" planarization (planarization across the entire wafer surface).
The other technique is planarization with resist or "resist etchback". One drawback to the etchback process is that a thicker ILD film must be deposited than will ultimately remain, since some is removed during the etchback step as described in S. Wolf, "Silicon Processing for the VLSI Era," vol. 2, Lattice Press, Sunset Beach, California, 1990, p. 234. Also, this technique requires more process steps in addition to typically requiring that the dielectric and resist have similar etch rates, which is difficult to accomplish and control.
In the SOG planarization process, the method requires the curing of spin-on-glass (SOG) layer, which converts the SOG to silicon dioxide. However, contaminants result when the structure is heated to greater than 300.degree. C., which evolve and corrode the aluminum vias.
To overcome some of the problems cited above, an improved planarization method known as chemical/mechanical polishing, or CMP, has been introduced. Here, a semiconductor wafer is held and rotated against a polishing surface, on which there is a polishing slurry containing abrasive material such as alumina or silica. At the same time, a chemical etchant may be introduced so that material is removed from the wafer by both chemical and mechanical means.
However, the mechanical polishing aspects of CMP is not much different from the common grinding and polishing techniques of similar processes using rotating machine heads, pads and abrasive slurries to polish glass and raw silicon wafers. Mechanical polishing introduces particle contaminants, and in the case of CMP where the slurry consists of hard to clean chemical solutions, contamination problem becomes even more acute. The problem is further compounded when polyimide is used as the interlevel dielectric.
As is well known in the art, polyimide films have some times been preferred as interlevel dielectrics because, as enumerated in S. Wolf, "Silicon Processing for the VLSI Era," vol. 2, Lattice Press, Sunset Beach, Calif., 1990, pp. 214-215, they have the various attractive properties such as: a) they produce surfaces in which the step heights of underlying features are reduced, and step slopes are gentle and smooth, b) the films are free of pinholes and cracks, and c) the process used to deposit and pattern the polyimide films is relatively simple, and less expensive compared to other alternatives. These advantages, however, are mitigated unless the following manufacturing-compatibility and reliability concerns are addressed: a) polyimide is hygroscopic (i.e., it readily absorbs water). Thus, if a wide metal line covers a portion of the polyimide film, the moisture under the metal film will attempt to escape the surface covered by the metal, which can lead to bubbling of the metal film, and b) the absorbed moisture can potentially cause corrosion of underlying metal lines. It will be appreciated by those skilled in the art, therefore, that when polishing a polyimide interlevel dielectric, the moisture content of the slurries used during polishing will lead to reliability problems unless preventive measures are taken to keep the slurry contaminants away from metal layers that are embedded within the polyimide layers.
In the prior art of polishing, slurry contaminants readily encroach upon layer structures as readily explained by referring to FIGS. 1a-1c. In FIG. 1a a plan view of a wafer (10) is shown. The wafer in the same figure has been subjected to many different process steps by methods well known in the art and as they are not significant to the invention, will not be described in detail here. The deposition of the various interlevel layers are also well known in the art and, therefore, are not described here in order not to unnecessarily obscure the present invention. It is sufficient to note from FIG. 1c that wafer (10) is comprised of substrate (60) and devices therein not shown, as well as metal layers also not shown but separated by means of interlevel dielectric the last one of which is polyimide layer (20) whose partial cross-section at 1c--1c is shown in the same FIG. 1c.
The polyimide layer on chip sites (20), which is also shown in the plan view of FIG. 1a, is patterned into scribe lines (30) by means of conventional lithographic processes. The scribe lines delineate chip sites, as will be well known to those who practice the art. Thus, the scribe lines form channels within the body of the interlevel dielectric (20), which are better seen in the enlarged plan view of FIG. 1b. The area in FIG. 1b corresponds to region (25) shown in FIG. 1a. Now, in order to further lap, or polish the back, or bottom side of substrate (60) prior to the final planarization of the dielectric layer on top, a grinding tape (40) is applied to the top side of the wafer. Again, tape (40) is better visualized in the cross-sectional view in FIG. 1b and is not shown in FIG. 1a for clarity.
In a typical polishing process of the back side of substrate (60), the taped top side (40) is held on a rotating carrier which in turn is held against a rotating polishing pad coated with a polishing slurry. Inasmuch as the scribe lines are relatively deep on the order of 5 micrometers, it has been observed in the present state of the manufacturing line that tape (40) cannot completely fill and seal the channels to prevent the polishing slurry (70) from entering the channels, and thereby causing the contamination of the polyimide layer (20). What is needed, therefore, is a method by means of which polishing contaminants can be kept away from reaching the polyimide layer on the wafer. Prior art does not address this need in polishing wafers. For example, U.S. Pat. No. 5,509,974 discloses only an etch control seal for dissolved wafer process. This is accomplished by bonding selected raised areas on a semiconductor substrate to a second substrate, hence forming trenches which in turn prevent the etchant solution to contact microstructures which are on the other side of the trench. However, this technique has the disadvantage of not being applicable to interlevel layers such as polyimides.